Digital Design Engineer

Company: SQL Pager LLC
Location: San Jose
Posted on: June 2, 2025

Job Description:

Job Description:

• Define block level micro-architecture and write design specification
• RTL implementation of the specification while meeting power, area, timing constraints
• Work with Verification team to verify functionality
• Work with Backend team to go through ASIC flow to tape-out success
• Work with Firmware teams to develop APIs and help silicon bring up
• Post-silicon validation and debugMinimal Qualifications:
• Master's degree in Electrical Engineering or related field
• 3 years of industrial experience in ASIC Design
• Experience in micro-architecture and RTL design of complicated blocks
• Proficient in RTL design using HDL
• Familiar with design and verification tools (VCS, Verdi, DC, etc.)
• Hands on experience of ASIC design flow including RTL design, verification, Lint, CDC, LEC, logic synthesis, DFT, timing analysis, floor-planning, GLS, ECO, bring-up & lab debug
• Proficient scripting language in one of: Python, TCL, Shell, Perl
• Self-motivated team workerPreferred Qualifications:
• Hands on design experience in PCIe logical / link / transaction layers.
• Knowledge of PCIe / CXL Protocol Stacks, especially latest Generations
• Experiences in SerDes architectures
• Experiences in Digital Signal Processing
• Good debugging and problem-solving skills
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Keywords: SQL Pager LLC, South San Francisco , Digital Design Engineer, Engineering , San Jose, California